Along with the rapid development of semiconductor manufacturing technologies, in order to gain faster calculation speed, larger data storage amount and more functions for a semiconductor device, semiconductor chips are improved to obtain higher integrity. However, the higher the integrity of the semiconductor chip, the smaller the Critical Dimension (CD) of the semiconductor device. In the 90 nm technique condition, the CD employed in a very large scale integrated circuit has reached the range from tens to hundreds of nanometers.
According to an Optical Proximity Correction (OPC) method, patterns on a photographic mask are corrected in advance, for example, a method which uses the Sub-Resolution Assist Feature (SRAF) as an assistant pattern on the photographic mask. The technical solution disclosed in Chinese Patent No. 95102281.4 is taken as an example. As shown in FIG. 1, in the circuit layout 1 of the Optical Proximity Correction software, a to-be-exposed assistant pattern 15 is added between adjacent to-be-exposed circuit patterns 10, where the to-be-exposed assistant pattern 15 is parallel to the to-be-exposed circuit pattern 10. The to-be-exposed assistant pattern 15 is a Sub-Resolution Assist Feature, for decreasing the intensity of light traveling between the adjacent to-be-exposed circuit patterns 10. Then, the to-be-exposed circuit pattern 10 and the to-be-exposed assistant pattern 15 having been designed in the OPC software are input into photographic mask manufacturing equipment. According to the sizes and positions of the input to-be-exposed circuit pattern 10 and to-be-exposed assistant pattern 15, the equipment can automatically generate a circuit pattern and an assistant pattern on the photographic mask using chrome layer or phase shifter. Here, the dimension of the to-be-exposed assistant pattern 15 is determined by the to-be-exposed circuit pattern 10, and generally, the width thereof ranges from 20 nm to 45 nm and the length from 80 nm to 120 nm. The width of the to-be-exposed assistant pattern 15 ranges from ⅖ to ⅘ of that of the to-be-exposed circuit pattern 10, and the length thereof is about 2 to 3 times of the difference resulted from the interval between adjacent to-be-exposed circuit patterns 10 minus the width of the to-be-exposed assistant pattern 15. When the assistant pattern on the photographic mask is reflected to the semiconductor substrate, because the dimension of the assistant pattern on the photographic mask is smaller than the resolution of the lithography equipment, a photo-resist film pattern corresponding to the assistant pattern will not be generated on the semiconductor substrate. Such a method of adding the Sub-Resolution Assist Feature is very suitable for correcting patterns relatively far away from each other to make them look denser, and increasing the Depth Of Field (DOF) of the exposed patterns which are far away from each other to improve the quality of the photos. Meanwhile, a dense pattern arrangement can greatly increase the freedom of process.
In the prior art, pattern lines are all straight lines or contain only right turning-angles. However, along with the continuously decreased dimension of the semiconductor device, using only the straight line or right turning-angle can not meet the requirements of pattern layout. Therefore, non-right turnings begin to be used in the pattern lines. Thus, when designing an OPC assistant pattern, it is required to collect proximity data of lines having various turning-angles to meet the requirements of designing the OPC assistant pattern.